PLDs are widely used for implementing digital logic. A PLD is configured for the desired circuit prior to use. For this purpose the PLD incorporates a configuration memory that defines its functional behavior based on data stored in it. Field Programmable Gate Arrays (FPGAs) are the most widely used PLD devices. A typical FPGA includes a matrix of logic blocks, routing resources and I/O blocks. In addition to this it also includes configuration memory cells and configuration control logic. Values stored in the memory cell control the operation of FPGA, i.e., functionality of FPGA is defined by the values stored in FPGA memory cells. Bits are loaded in the configuration memory cells through a configuration logic that is provided by configuration devices.
FIG. 1 defines a conventional FPGA configuration process flow as described in ALTERA's application note 116 “Configuring APEX20K, FLEXI OK, FLEX6K devices, ALTERA's application note 33 “Configuring FLEX8K devices”, Virtex's application note XAPP138 “FPGA Series Configuration and Readback” and Xiinx. Inc.'s “The programmable Logic databook 1999”. The FPGA is first brought into the configuration mode 100, following which the configuration memory is cleared 102. The configuration memory is cleared by storing 0's or 1's in all the cells of the memory. In case of partial configuration, configuration memory is not cleared and step 102 is bypassed. In step 104, configuration data is loaded frame by frame. After each frame is loaded, an error detection circuit checks the frame for any error in step 106. There are several methods for checking the frame for errors such as parity check, Cyclic Redundancy Check (CRC) etc., but the most popular method is a CRC check. If no error is detected in the frame, then the process moves onto step 108 to check whether the end of configuration process has been reached or not. If the configuration process is not over, i.e., more frames are still to be loaded, the process flow reverts to step 104 and the next frame is loaded. Subsequently steps 106 and 108 are followed again until the end of configuration of the FPGA. When the end of configuration is reached, the FPGA device comes back to the start up mode as shown in step 110. After the device is configured it can start its normal operation.
If any error is detected in the data frame at step 106, the STATUS signal is set into the ‘High’ state in step 107, indicating an error in the data frame. The configuration is stopped and the process restarts all over again from step 100 and all the frames are reloaded again. This method of configuration of a FPGA device is inefficient because even if an error occurs in the last frame to be loaded to the device, all the frames successfully loaded prior to that frame have to be loaded again, leading to wastage of time.